1. Field of the Invention
The present invention relates to a dynamic read amplifier for metal-oxide-semiconductor (MOS) memories having a flip-flop comprising two first switching transistors whose low end can be applied to ground via a cut-through transistor by way of a first clock pulse and whose outputs are connected to the information lines via cut-off transistors controlled by a second clock pulse, whereby the information or data lines can be charged to the supply voltage via a pair of charging transistors by way of a third clock voltage.
2. Description of the Prior Art
In MOS memory modules having single-transistor memory cells, small signals must be amplified with a read amplifier. The read amplifiers are constructed as flip-flops and, given dynamic operation, use the data lines as a voltage supply. For this reason, given signal amplification, the signal level for a logical "1" on the data lines is lowered and only a lower potential can be rewritten into the memory cell. In the next read-out cycle, this leads to a diminished read signal.
With static read amplifiers, instead of dynamic read amplifiers, the signal level for a logical "1" is regenerated, but the forward current occurring upon discharge of the signal line for the logical "0" leads to an inadmissibly high leakage power. Heretofore, signal level regeneration was not employed in dynamic read techniques.